cpu-architecture

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Different runtimes for aligned vs unaligned memory access on x86_64 and ARM64
user_5800830
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4
0
242
arm64 x86-64 memory-alignment cpu-architecture performance
What data will be cached?
user_143280980
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2
2
651
cpu-cache cpu-architecture caching c c++
How does Java Handle Endianess when running on Little Endian CPU Architectures?
user_6766440
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3
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321
openj9 endianness cpu-architecture java performance
Invalid results querying my system’s cache information with GetLogicalProcessorInformation()
user_17578050
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3
1
96
cpu-cache x86 cpu-architecture winapi c++
What does memory_order_consume really do?
user_101666630
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7
3
1130
stdatomic memory-model lock-free cpu-architecture c++
How does DC PMM (memory mode) cache coherence behave?
user_113380060
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4
1
271
persistent-memory cpu-cache intel x86 cpu-architecture
Can a fully associative cache have a higher miss rate than a direct mapped cache?
user_145515950
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2
1
1090
cpu-cache cpu-architecture caching
Assembly register vs CPU register
user_134567710
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2
1
114
cpu-registers assembly cpu-architecture
Are snoop requests sent to all the cores in a multi node setup?
user_113380060
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2
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138
cpu-cache intel x86 cpu-architecture
Problem with the information displayed by the cpuid command
user_143280980
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2
2
167
cpuid cpu-cache x86 cpu-architecture caching
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