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C# compiled into assembly. Why does it take longer to run fewer assembly instructions?
user_103959
0
•
asked Jan 23, 2021
4
0
90
amd-processor
x86-64
assembly
cpu-architecture
c#
C++ calling convention for passing big objects on Linux/x86-84
user_14333280
0
•
asked Jan 22, 2021
6
1
214
x86-64
calling-convention
assembly
linux
c++
Non-temporal store to bypass L1/L2 but cache in L3 to be read by another core
John_Zwinck_4323
0
•
asked Jan 19, 2021
2
0
170
x86-64
cpu-cache
assembly
caching
multithreading
Why does this function run so much faster when it makes an extra read of memory?
user_11875845
0
•
asked Jan 17, 2021
16
1
332
x86-64
clang
assembly
cpu-architecture
performance
PMC to count if software prefetch hit L1 cache
user_11322131
0
•
asked Jan 16, 2021
3
1
270
intel-pmu
memory-barriers
x86-64
performancecounter
intel
Why "mov %%rsp, %%rbp" causing Segmentation fault?
user_14090817
0
•
asked Jan 13, 2021
3
2
786
x86-64
inline-assembly
segmentation-fault
c
Understanding factors in latency bounded memcpy/memset x86_64
user_11322131
0
•
asked Jan 11, 2021
2
0
159
memory-bandwidth
memcpy
x86-64
intel
cpu-architecture
x86 SIMD instructions 16 byte alignment in assembly (Without C intrinsics)
user_14152996
0
•
asked Jan 10, 2021
3
1
685
x86-64
simd
memory-alignment
sse
assembly
On x86-64, is the “movnti” or "movntdq" instruction atomic when system crash?
user_14883676
0
•
asked Jan 4, 2021
5
1
521
persistent-memory
x86-64
atomic
sse
cpu-architecture
Does a Length-Changing Prefix (LCP) incur a stall on a simple x86_64 instruction?
user_4603507
0
•
asked Jan 1, 2021
4
1
399
x86-64
micro-optimization
assembly
cpu-architecture
performance
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