micro-architecture

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Do cache block replacement policies in x86 prefer clean blocks over dirty blocks?
user_60902260
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micro-architecture x86-64 cpu-cache cpu-architecture
The execution process of the instruction and the realization in gem5?
user_143280980
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297
micro-architecture gem5 instructions x86 cpu-architecture
Why did Intel remove the 16-byte branch target alignment Coding Rule from the Optimization Reference Manual?
user_46035070
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131
micro-architecture x86-64 micro-optimization intel x86
Way prediction in modern cache
user_49722960
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1875
micro-architecture cpu-cache processor cpu-architecture caching
Any reason to use BX R over MOV pc, R except thumb interwork pre ARMv7?
user_9041480
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952
micro-architecture branch-prediction arm assembly cpu-architecture
Execute operations of the same instruction separately in an OoO processor
user_137279120
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97
micro-architecture instructions x86 assembly cpu-architecture
Intel JCC Erratum - should JCC really be treated separately?
user_29450270
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610
micro-architecture intel x86 assembly cpu-architecture
Are two store buffer entries needed for split line/page stores on recent Intel?
user_1491380
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micro-architecture micro-optimization intel x86 cpu-architecture
How do the store buffer and Line Fill Buffer interact with each other?
user_5820100
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cpu-mds micro-architecture cpu-cache x86 cpu-architecture
How many ways-superscalar are modern Intel processors?
user_58107470
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1898
micro-architecture intel x86 cpu-architecture
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