micro-architecture

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Will CPUID serialize speculative data caching?
user_108656220
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cpuid micro-architecture microbenchmark cpu-cache x86
Why jnz requires 2 cycles to complete in an inner loop
user_108656220
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micro-architecture microbenchmark micro-optimization x86
Weird performance effects from nearby dependent stores in a pointer-chasing loop on IvyBridge. Adding an extra load speeds it up?
user_108656220
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micro-architecture microbenchmark micro-optimization x86 assembly
Is mov r64, m64 one cycle or two cycle latency?
user_108656220
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micro-architecture microbenchmark cpu-cache x86 assembly
Why dependency in a loop iteration can't be executed together with the previous one
user_108656220
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micro-architecture micro-optimization x86 assembly performance
When making read request to DRAM, why we need to read tag and data, not data only?
user_106270590
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micro-architecture cpu-cache memory cpu-architecture
What are my available march/mtune options?
user_45263360
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micro-architecture compiler-flags x86 gcc command-line
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