memory-barriers

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Request for review of memory orders of mpsc queue
user_14870690
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2
1
128
stdatomic memory-barriers memory-model thread-safety c++
What are the exact inter-thread reordering constraints on mutex.lock() and .unlock() in c++11 and up?
user_155661210
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7
2
360
memory-barriers language-lawyer mutex c++11 c++
Can't relaxed atomic fetch_add reorder with later loads on x86, like store can?
user_117746080
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4
3
355
stdatomic memory-barriers cpu-architecture multithreading c++
(Persistence) ordering of Intel non-temporal stores to the same cache line
user_72896060
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5
1
216
persistent-memory memory-barriers x86 cpu-architecture
Do atomic operations in Go make sure other variables are visible to other threads?
user_54748140
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4
2
1090
memory-barriers go memory-model
Why “movnti” followed by an “sfence” guarantees persistent ordering？
user_148836760
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3
1
159
persistent-memory memory-barriers x86 cpu-architecture
PMC to count if software prefetch hit L1 cache
user_113221310
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3
1
270
intel-pmu memory-barriers x86-64 performancecounter intel
Behavior of breakpoint on relaxed memory models
user_57902510
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2
1
61
memory-barriers x86 breakpoints
For purposes of ordering, is atomic read-modify-write one operation or two?
user_6349190
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11
1
395
stdatomic memory-barriers atomic c++
Does a relaxed memory-order spinlock always break synchronization?
user_50014480
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4
1
111
stdatomic memory-barriers atomic c++
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