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Understanding factors in latency bounded memcpy/memset x86_64
user_11322131
0
•
asked Jan 11, 2021
2
0
159
memory-bandwidth
memcpy
x86-64
intel
cpu-architecture
Does Intel MKL redefine functions from math.h in C?
user_9555794
0
•
asked Jan 2, 2021
2
0
60
math.h
intel
compilation
c
performance
How does DC PMM (memory mode) cache coherence behave?
user_11338006
0
•
asked Dec 16, 2020
4
1
271
persistent-memory
cpu-cache
intel
x86
cpu-architecture
Are snoop requests sent to all the cores in a multi node setup?
user_11338006
0
•
asked Dec 13, 2020
2
1
138
cpu-cache
intel
x86
cpu-architecture
MacOS Big Sur : impossible to compile with a C++ code with Intel compiler
user_1773603
0
•
asked Dec 11, 2020
2
0
1211
icc
compiler-errors
intel
compilation
macos
How do I see how many slices are in the last level cache?
user_14328098
0
•
asked Dec 8, 2020
3
1
522
cpu-cache
intel
x86
cpu-architecture
caching
r/m8 operand being interpreted as r/m32 operand by disassembler
user_11520390
0
•
asked Dec 2, 2020
2
0
76
disassembly
intel
x86
reverse-engineering
assembly
Intel-TSX: why rtm is acting weird?
user_14090817
0
•
asked Nov 25, 2020
2
0
90
intel-tsx
intel
makefile
c
Why are set cache associativity in modern day processors 8-way set associative?
user_13170122
0
•
asked Nov 12, 2020
3
1
1092
amd-processor
cpu-cache
intel
cpu-architecture
caching
Why is POP slow when using register R12?
user_10461973
0
•
asked Nov 11, 2020
7
1
293
micro-optimization
intel
x86
cpu-architecture
performance
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