cpu-architecture

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Benchmarking cache latency with a C/Assembly program, why do my caches appear to be 8x?
user_32071540
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154
cpu-cache assembly memory cpu-architecture c
Does the fetch phase in the x86 CPU increment eip(PC) to the next instruction?
user_167253990
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2
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101
program-counter x86 assembly cpu-architecture
Instruction which results in 0 but isn't dependency-breaking
user_64696900
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4
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73
microbenchmark x86 assembly cpu-architecture
Why is there only little difference in integer division throughput with larger values on AMD Zen?
user_64696900
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3
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184
integer-division x86 assembly cpu-architecture performance
Run time and reported cycle counts in linux perf
user_8592270
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2
1
272
perf matrix-multiplication x86-64 cpu-architecture performance
Are IA-32 segment descriptors that do not cover the full 4GiB linear address space slower?
user_148462760
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2
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43
memory-segmentation x86 cpu-architecture optimization performance
handling x86-64 microarchitecture levels in Debian package names
user_120112940
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3
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109
micro-architecture debian-packaging x86-64 debian cpu-architecture
Where do the values of uninitialized variables come from, in practice on real CPUs?
user_174514110
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4
4
307
assembly cpu-architecture c
Can L2 software prefetches trigger L2 hardware prefetch?
user_31549960
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7
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114
prefetch x86 cpu-architecture optimization performance
Would an Instruction Set Architecture benefit from both an ADC and SBC, or could all carry instructions repeat the previous type?
user_102355350
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4
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54
carryflag instruction-set assembly cpu-architecture
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