Why A and B registers are used in multicycle Datapath?

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Why are registers A and B whose inputs are ReadData1 and ReadData2 of RegisterFile are necessary? Isn't it possible to use directly the values which are on ReadData1 and ReadData2 outputs of Register File?

Instruction Register is already loaded with an instruction, so the value of IR is fixed, which means that $rs, $rt, $rd reg numbers are obviously the same within a single instruction. Hence, there are always the same values on the ReadRegister1 and ReadRegister2 inputs of the Register File. So the values that are on RD1 and RD2 outputs are the same unless the corresponding registers inside RegisterFile are overwritten.

That means that A and B registers are necessary only for the instructions that require to have the values of $rs or $rd registers that were overwritten on previous cycle. Can anybody give me an example of such an instruction.

spim mips cpu-registers cpu-architecture
1 Answers

The general pattern is that during a clock cycle: at the start of the clock, some register(s) feed values to computational logic which feed values to (the same or other) register(s) by the end of the clock, so that it can start all over again for the next cycle.

In the single cycle datapath, the value in the PC starts the process of the cycle, and by the end of the cycle, the PC register is updated to repeat a new cycle with another value.  Along the way, the register file is both consulted and also (potentially) updated.  You may note that these A & B registers are not present in the single cycle datapath.

You are correct that those values do not change during the execution of any one single instruction on the multicycle datapath.

However, the multicycle processor uses multiple cycles to execute a single instruction (so that it can speed the clock).  In order to support the successive cycles in that processor design, some internal registers are used — they capture the output of a prior cycle in order for a next cycle to do something different.

The problem with the multicycle datapath diagrams is that they don't make it clear what part of the processor runs in what cycles.  Those A & B registers are there to support a cycle boundary, so the decode is happening in one cycle and the arithmetic/ALU in another cycle.  (Without those registers, the processor would have to perform decode again in the subsequent cycle, which would decrease the clock rate and defeat the nature of the multicycle datapath.)

Boundaries are made much more clear in pipeline datapath diagrams.  Search for "MIPS pipeline datapath".  (Note that some pipeline datapath diagrams show registers between stages and others simply outline what's in what stage without showing those registers.)  The large vertical bars are registers and they separate the pipeline stages.  Of course, the pipeline processor executes all pipeline stages in parallel, though in theory, similar boundaries are applicable to the cycles in a multicycle processor.  Note that the ID/EX pipeline register in the pipeline datapath serves the purpose of the A & B registers in the multicycle datapath.

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