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cpu-architecture
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Does the ARM processor have invalidate queue?
user_2351818
0
•
asked Jul 2, 2017
5
0
129
arm
processor
cpu-architecture
multithreading
What is the purpose of the reserved/undefined bit in the flag register?
user_6352200
0
•
asked Jun 30, 2017
5
1
2036
8085
intel-8080
z80
x86-16
cpu-architecture
Interpreting CISC as RISC
user_7936230
0
•
asked Jun 4, 2017
3
2
565
x86
assembly
cpu-architecture
Can someone explain this about paging in operating system?
user_7845429
0
•
asked Jun 4, 2017
4
2
1568
paging
operating-system
cpu-architecture
memory-management
ARM vs x86 What are the key differences?
user_6135019
0
•
asked May 30, 2017
4
2
5700
arm
instruction-set
x86
cpu-architecture
cpu
Can x86's MOV really be "free"? Why can't I reproduce this at all?
user_541686
0
•
asked May 24, 2017
41
2
5832
micro-optimization
x86
assembly
cpu-architecture
c
What does "nop dword ptr [rax+rax]" x64 assembly instruction do?
user_843732
0
•
asked May 16, 2017
20
3
8790
no-op
x86-64
assembly
cpu-architecture
visual-studio
Perf collect stats
user_950238
0
•
asked Mar 26, 2016
3
0
247
perf
performancecounter
cpu-architecture
Why we do not use barriers in User space
user_3420919
0
•
asked Mar 22, 2016
3
3
1495
barrier
memory-barriers
cpu-cache
cpu-architecture
memory-management
How to divide by 9 using just shifts/add/sub?
user_379071
0
•
asked Mar 21, 2016
8
2
2276
integer-arithmetic
assembly
cpu-architecture
algorithm
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