cpu-architecture

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Where does the scheduler run?
user_42162330
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6
3
3193
scheduler cpu-architecture
How exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistent
user_2241320
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46
2
3304
micro-optimization intel x86 assembly cpu-architecture
Why are registers needed (why not only use memory)?
user_84374630
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10
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4767
cpu-registers x86 assembly cpu-architecture
Calculating execution time for 2-threaded CPUs?
user_84114540
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3
1
93
operating-system cpu-architecture multithreading
Lost Cycles on Intel? An inconsistency between rdtsc and CPU_CLK_UNHALTED.REF_TSC
user_1491380
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34
1
3185
rdtsc x86-64 x86 cpu-architecture performance
How do the costs of atomic operations vary across architectures?
user_80681760
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3
0
272
c11 compare-and-swap atomic c++11 cpu-architecture
Why is the x86 CR1 control register reserved?
user_32414870
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10
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1136
intel x86 cpu-architecture
What percentage of Android phones are little-endian?
user_40772940
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4
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2653
endianness cpu-architecture android java
Was there a P4 model with double-pumped 64-bit operations?
user_1491380
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5
1
750
x86-64 intel x86 cpu-architecture
How would the MONITOR instruction (_mm_monitor intrinsic) be used by a driver?
user_82783940
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3
1
2433
driver smp x86 cpu-architecture
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