I'm preparing for a test in computer science and there's this question that keeps coming up in previous tests that I can't find an answer to.
Consider the execution of the two instructions below on a typical RISC architecture with only one addressing mode (Reg + Offset).
804836e: 40 inc %eax
804836f: 89 04 91 mov %eax,(%ecx,%edx,4)
Explain, justifying, how these 2 IA-32 instructions would be compiled for this architecture, using IA-32 sintaxe to show that code.
Comment on the size of this piece of code on the RISC architecture versus the IA-32.
The C function is :
voidpara_par (int a[], int n) {
int i;
for (i=0 ; i<n ; i++) {
if (a[i] & 0x01) {
a[i] += 1;
}
}
}
Which receives an array of ints and increments the value of the odd ones.
For reference:
%eax -> int i
(%ecx,%edx,4) -> int, part of the array "a" saved to %ecx
I know this question feels vague to say the least but that's my problem, I don't really know how to begin "translating" from one architecture to the other.