cpu-architecture

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Does Program Counter hold current address or the address of the next instruction?
user_12843110
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9
4
6764
program-counter assembly cpu-architecture
SIMD intrinsic and memory bus size - How CPU fetches all 128/256 bits in a single memory read?
user_41235770
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2
1
546
memory-bandwidth x86-64 simd sse cpu-architecture
Can a hyper-threaded processor core execute two threads at the exact same time?
user_54643830
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3
1
1629
hyperthreading cpu-architecture multithreading multiprocessing
What specifically marks an x86 cache line as dirty - any write, or is an explicit change required?
user_4060680
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13
3
1537
memory-bandwidth x86-64 cpu-cache x86 cpu-architecture
How to create branchless code for this piece of code?
Admin1
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4
2
1865
compiler-optimization micro-optimization computer-science cpu-architecture compiler-construction
Calculating memory size based on address bit-length and memory cell contents
user_86806270
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6
1
45805
memory-address memory cpu-architecture
TensorFlow: CPU Choice AVX-512 AMD, Intel?
user_3772520
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4
0
3736
tensorflow cpu-architecture cpu
Does the VMX mode have the capability to detect previously non-trappable sensitive instructions?
user_81861130
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3
2
273
intel x86 processor cpu-architecture
Implementation of chrono library
user_78702090
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2
1
869
cpu-architecture time c++
Virtually indexed physically tagged cache Synonym
user_58417270
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7
1
2745
operating-system cpu-cache cpu-architecture caching
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