cpu-architecture

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Is Zero Register 'zr' in aarch64 essentially ground?
user_10283410
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6
5
2550
arm64 zero cpu-registers assembly cpu-architecture
Pipeline on Registers calculation
user_96720930
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6
3
508
x86 assembly cpu-architecture c++
Assembly - How to score a CPU instruction by latency and throughput
user_101158470
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3
1
2112
micro-optimization x86 assembly cpu-architecture performance
how is CPU physical address space mapped to physical DRAM?
user_102509940
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6
1
1942
mmu memory-address x86 memory cpu-architecture
How does MIPS r10000 fetch hide instruction cache latency?
user_26099230
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4
1
317
mips processor cpu-architecture
How is load->store reordering possible with in-order commit?
user_35048870
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11
1
1974
memory-barriers arm cpu-architecture
Is test-and-set (or other atomic RMW operation) a privileged instruction on any architecture?
user_71549240
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4
1
2523
futex operating-system assembly cpu-architecture linux
How to record a timestamped trace of every memory access?
user_102954630
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3
3
1262
perf memory cpu-architecture linux
Memory latency measurement with time stamp counter
user_8592270
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3
2
1303
tsc x86 cpu-architecture c performance
Can the LSD issue uOPs from the next iteration of the detected loop?
user_58016610
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9
1
420
intel-pmu x86 assembly cpu-architecture
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