How to display data from memory file at the positive edge of the clock?

user_15421811 0
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I have a text file with hexadecimal data. I want to display the data at only the positive edge of the clock, thus controlling the frequency of the data. I have written the following code:

module testbench;
    reg [15:0] in[0:5];
    reg clk;
    integer i;
    initial
     clk=1'b0;
     always
      #5 clk = ~clk;
    
    initial
      $readmemh("Input_rsvd.dat",in);
      always @ (posedge clk)
      begin
       for(i=0;i<5;i=i+1)
        $display( "result = %h",in);
      end
endmodule

Obviously, the code has some problem which I can not figure out. Can anybody help me with this?

test-bench hdl verilog
1 Answers

When I try to run your code, I get a compile error on multiple simulators. You can not pass a memory variable to $display like that. I think you intended to print one value at a time. To fix it, change:

    $display( "result = %h",in);

to:

    $display( "result = %h",in[i]);

Also, if you want to print all 6 values, change:

   for(i=0;i<5;i=i+1)

to:

   for(i=0;i<6;i=i+1)

Here is the new code, using a more consistent layout:

module testbench;
    reg [15:0] in [0:5];
    reg clk;
    integer i;

    initial clk = 1'b0;

    always #5 clk = ~clk;
    
    initial $readmemh("Input_rsvd.dat", in);

    always @(posedge clk) begin
       for (i=0; i<6; i=i+1) $display("result = %h", in[i]);
    end
endmodule
user_1977580
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