Quartus Failure for initialization ROM memory by using $readmemh task

Kun liu 0
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I initialized my ROM memory (instr_mem) by using the $readmemh task. The ROM was successfully complied and simulated, but the waveform show 32'hxxxxxxxx in instr_mem. It seems the 'instr_mem' didn't get the value from mem_instruction.txt file.

module mips_mem(addr1,data_in1,data_out1,we1,
    addr2,data_in2,data_out2,we2,
    rst_b,clk);

// Boundaries and lengths of each segment
// Note that '_top' addresses off by one; the actual top is one less
//      than the values below.
// '_w' values are word addresses

input         rst_b;
input         clk;

// Inputs and ouptuts: Port 1
input [5:0]  addr1;         // Memory address
input [31:0]  data_in1;      // Memory write data
output [31:0] data_out1;     // Memory read data
reg [31:0]   data_out1;
input [0:3]      we1;           
     

// Inputs and outputs: Port 2
input [5:0]  addr2;         // Memory address
input [31:0]  data_in2;      // Memory write data
output [31:0] data_out2;     // Memory read data
reg [31:0]   data_out2;
input [0:3]  we2;          


// Memory segments
reg [31:0]   data_mem[0:63];
reg [31:0]   instr_mem[0:63];

 // Verilog implementation stuff
 integer     i;
 wire [31:0] write_mask1 = {we1[3], we1[3], we1[3], we1[3],
                  we1[3], we1[3], we1[3], we1[3],
                we1[2], we1[2], we1[2], we1[2],
                we1[2], we1[2], we1[2], we1[2],
                we1[1], we1[1], we1[1], we1[1],
                we1[1], we1[1], we1[1], we1[1],
               we1[0], we1[0], we1[0], we1[0],
              we1[0], we1[0], we1[0], we1[0]};


// Handle Port 1 Read
initial
 begin

$readmemh("mem_instruction.txt", instr_mem);
 end
always @(posedge clk or negedge rst_b) begin
     if(rst_b==1'b0) begin
          data_out1 <= 32'hxxxxxxxx;  
      end
      else begin
          data_out1 <=instr_mem[addr1];
      end
 end

endmodule

The screenshort of waveform enter image description here enter image description here

verilog intel-fpga quartus fpga system-verilog
1 Answers

Add this code snip to the mips_mem module to determine if the memory style variable is getting the file contents.

initial
 foreach(instr_mem[i])
  $display("instr_mem[%0d] = %0h",i,instr_mem[i]);

If this prints the memory contents then its not a problem of file location (another issue??).

If this prints x's then issue is probably that the simulator needs help finding the file.
Use a simlink to the .txt file in the directory where the simulation is executing.

Mikef0
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