zynq

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Is there a way to synchronize custom interrupt signals with AXI master transactions in Vitis HLS?
user_15263210
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4
1
199
axi4 zynq xilinx vivado interrupt
How to access XDMA BAR0 in Petalinux?
user_11615840
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1
1
131
zynq-ultrascale+ petalinux zynq xilinx dma
How To Convert .bit file to .bin
user_111422800
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1
1
831
xsdk zynq xilinx fpga
/dev/mem or user space burst transfer; how to get faster /dev/mem access
user_38272770
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2
1
782
zynq xilinx embedded-linux
Zynq, Yocto Linux and Custom FPGA IP Block Workflow
user_31771080
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2
1
487
zynq yocto driver fpga linux
Zynq 7000: Minimum asm code to init cpu1 from cpu0
user_2796100
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3
1
442
cortex-a zynq armv7 assembly
Boot fail on zynq ultrascale+ mpsoc zu3eg on the ULTRA 96
user_113911530
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2
0
275
petalinux zynq xilinx boot
Vivado, Zynq, BRAM Controller, Narrow AXI burst option
user_41605600
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5
1
664
axi4 zynq xilinx vivado
Xilinx, Zynq, AXI4 interconnect. What are the performance implications of configuring register slice and data fifo options?
user_41605600
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3
1
1186
axi4 zynq xilinx vivado
AXI Protocol, difference between secure and non-secure transactions
user_41605600
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5
1
1017
axi4 zynq vivado
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