Consider a simple system with PS (Processor system) with enabled AXI3 Master, connected to AXI4 Interconnect connected to BRAM Controller that has access to BRAM memory.
What is the meaning of AXI Narrow Bursts? How do i define or consider what is narrow burst? Can i control whether I want a narrow burst or not?
Narrow burst allows transfer of data smaller than the data bus width. The main use use to allow slave devices of differing bus widths, or requests of a smaller width, to to communicate with the master.
Please see AXI4 (Lite) Narrow Burst vs. Unaligned Burst Clarification/Compatibility The accepted answer gives a good description.
