SpiceQA
Questions
Tags
Users
Badges
x86
1199 Questions
Newest
Active
Unanswered
Frequent
More
Score
View
Card
Compact
PCI I/O BAR Addresses - 32-bit or 16-bit?
user_7275390
0
•
asked Jun 22, 2021
2
1
289
base-address
pci
osdev
x86
How to help GCC to not insert xor before lzcnt?
user_15853075
0
•
asked Jun 21, 2021
4
0
95
clang
x86
assembly
gcc
c++
Why XOR before SETcc?
user_15853075
0
•
asked Jun 18, 2021
4
1
272
micro-optimization
x86
assembly
c++
"hlt"-instruction ignored/skipped in my x86_64 boot code (when I test it in QEMU)
user_2891595
0
•
asked Jun 17, 2021
1
1
131
osdev
qemu
x86
Is the address checked by the memory alignment check mechanism a effective address, a linear address or a physical address?
user_16242278
0
•
asked Jun 16, 2021
7
1
299
memory-segmentation
osdev
memory-alignment
x86
assembly
What happens to the CPU pipeline when the memory with the instructions is changed by another core?
user_33364
0
•
asked Jun 15, 2021
2
2
237
hotpatching
pipeline
x86
assembly
cpu-architecture
multiboot2 header to properly go into "EFI amd64 machine state with boot services enabled" - hlt instruction not working?
user_2891595
0
•
asked Jun 15, 2021
1
1
257
multiboot
grub
nasm
x86-64
x86
qemu x86_64 enable protect mode and jmp far, causes reboot
user_14343272
0
•
asked Jun 15, 2021
2
0
72
qemu
operating-system
x86
Atomic operation contention between SMT/HT Threads
user_309807
0
•
asked Jun 13, 2021
2
0
95
compare-and-swap
atomic
hyperthreading
x86
cpu-architecture
Why is clflush an unprivileged instruction in x86?
user_9027541
0
•
asked Jun 11, 2021
2
0
116
cpu-cache
x86
cpu-architecture
Prev
Prev
31
32
33
(current)
34
35
Next
Next
Hot Questions