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How many ways-superscalar are modern Intel processors?
user_5810747
0
•
asked Oct 16, 2019
5
1
1898
micro-architecture
intel
x86
cpu-architecture
Low performance with CLWB (cacheline write-backs) to same location vs. cycling through a few lines
user_2212968
0
•
asked Oct 11, 2019
5
1
341
intel
x86
memory
c++
performance
Debian 10 (Buster) slow desktop/GUI
user_6524000
0
•
asked Oct 7, 2019
4
4
9965
debian-buster
driver
nvidia
intel
Linker error when C++ executable links in Fortran library and main in C++ library
user_1782465
0
•
asked Oct 4, 2019
3
1
295
intel
fortran
cmake
linker
c++
SIMD instructions lowering CPU frequency
user_9784373
0
•
asked Jul 2, 2019
51
2
10722
avx512
compiler-optimization
intel
x86
optimization
Instrumenting QEMU instance with Intel Pin Tool
user_3382741
0
•
asked Jun 30, 2019
3
0
226
intel-pin
kvm
instrumentation
x86-64
intel
Converting to and from __m256i and std::vector<uint32_t>
user_149138
0
•
asked Jun 23, 2019
5
1
934
avx2
intrinsics
simd
intel
c++
Temporal locality in memory mountain
user_2875210
0
•
asked Jun 23, 2019
3
1
910
cpu-cache
intel
x86
cpu-architecture
performance
Can different processes run RDTSC at the same time?
user_4675668
0
•
asked Jun 4, 2019
5
1
395
rdtsc
hyperthreading
multicore
intel
x86
What level of the cache does PREFETCHT2 fetch into?
user_149138
0
•
asked Jan 15, 2019
4
0
289
amd-processor
cpu-cache
intel
x86
cpu-architecture
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