How to generate verilog code like "reg[n-1:0] = 90" with chisel3?

Reset is implicit in Chisel Module, all Reg will have a reset. Then initial value will be set at reset following code

val myreg = RegInit(90.U((n-1).W))

But, for FPGA without reset input, we can generate it with a BlackBox with Verilog "inline" like this module :

class ResetGen extends BlackBox with HasBlackBoxInline {
  val io = IO(new Bundle {
    val clk = Input(Clock())
    val rst = Output(Bool())
  })

  setInline("ResetGen.v",
    s"""
    |module ResetGen(
    |    input clk,
    |    output rst
    |);
    |
    |reg reset_reg = 0;
    |reg [7:0] reset_dly_cnt = 0;
    |always@(posedge clk) begin
    |  if(reset_dly_cnt < 8'hff)
    |      reset_dly_cnt <= reset_dly_cnt + 1'b1;
    |  else
    |      reset_reg <= 1;
    |end
    |
    |assign rst = !reset_reg;
    |endmodule
    """.stripMargin)
}

Then add the connexion in your Top :

class TopMyModule extends RawModule {
  val gclk = IO(Input(Clock()))
//...
  /* Generate the reset pulse */
  val rst = Wire(Bool())
  val rstgen = Module(new ResetGen())
  rstgen.io.clk := gclk
  rst := rstgen.io.rst

  /* Wrap all in gclk, rst domain */
  withClockAndReset(gclk, rst) {
      val myreg = RegInit(90.U((n-1).W))
//..

myreg will be initialized to 90 when rst signal is at 1.