Best way to define and initialize matrix in VHDL

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I'm trying to make a program that uses matrices( 2d arrays) of integers in vhdl and i have never done that before.

First of all, is it possible to define a 2d array in the entity's signal definitions?What I mean is something like this;

entity Matrix is 
Port ( CLK : in STD_LOGIC;
       RESET : in STD_LOGIc;
       Output : out array (integer range <> , integer range <> ) of integer);
end Matrix;

Also. What is the best way to actually initialize a matrix ? I thought of doing something like this;

type 2d_array is array(2 downto 0, 2 downto 0) of integer;

constant A2d : 2d_array :=((1,2,3),
                            (1,2,3),
                            (1,2,3));

Still, I'm not really sure if that is correct.

Last but not least, what would happen if i tried to rashape one of the output matrices into an 1-D array? Whould that solve my first problem, or would that create a new one ?

vivado fpga vhdl
1 Answers

In VHDL, all types must be declared before use. So you cannot simply declare an object as an "array" because you have not declared the type yet. To use a type in an entity port definition, you would usually need to declare the type in a package, and include the package in the entity.

package my_types_pkg is
  type my_array_t is array(integer range <>, integer range <>) of integer;
end package;

use work.my_types_pkg;

entity Matrix is 
Port ( CLK : in STD_LOGIC;
       RESET : in STD_LOGIc;
       output : out my_array_t -- note this is not yet constrained - the object mapped to this port will constrain the port
     );

Initialisation : You did the correct thing for a 2d array.

"Reshaping" : VHDL is a strongly typed language. So arrays are not necessarily directly convertible. A 2D array of integers is not the same type as a 1D array of integers, and hence a type conversion function will be required.

user_85672310
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