About Me
// Hello, World !
Top Answers
-
What is the advantage of using a testbench rather than a ".do" file in ModelSim?
5 votes
-
Can we write to two signals from a port map statement?
4 votes
-
Best way to define and initialize matrix in VHDL
4 votes
-
Meaning x"00" in VHDL
3 votes
-
Initializing arrays in VHDL: How exactly does it work?
3 votes
Top Questions
-
Can you alias an entity?
4 votes1 answers
-
Gitlab runners won't kill cancelled jobs
4 votes0 answers
-
Initial Value Default for Generic with a Generic Type
4 votes0 answers
-
Pattern Matching for rules parameter Gitlab CI
3 votes2 answers
-
"Pure" and "Impure" functions - what's the point?
3 votes0 answers