Getting an error using parameter in Verilog

user_16852521 0
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I’m new to using verilog for verifying memories. I’ve defined address width and data width in the testbench as parameters, and I’m trying like this below which is giving me an error:

parameter ADDRESS_WIDTH =9

And down below in the testbench somewhere, I’m calling tasks:

Read_mode(ADDRESS_WIDTH’134)

I’m getting an error with this. Please help.

test-bench verilog
2 Answers

ADDRESS_WIDTH’134 produces a syntax error because it is illegal to use a parameter for a numeric literal size like that, and when you use the apostrophe, it must be followed by a base specifier (such as h for hexadecimal format). Also, the apostrophe character in your question might be a problem depending on how you copy and paste it into an editor.

To pass a numeric literal to a task, it is not necessary to specify the bit width of the value because that can be accounted for when you declare the task input. You can declare the input with the desired bit width, then pass the numeric value with just the base specifier, such as 'h134 for a hexadecimal value:

module tb;

parameter ADDRESS_WIDTH = 9;

task Read_mode (input [ADDRESS_WIDTH-1:0] addr);
    $displayh(addr);
endtask

initial begin
    Read_mode('h134);
    Read_mode(134);
    Read_mode('hfff);
end

endmodule

Prints:

134
086
1ff

Note that 134 (without the base) is a decimal value, and that values larger that 9 bits ('hfff) will be forced to 9 bits (1ff).

Refer to IEEE Std 1800-2017, section 5.7.1 Integer literal constants.

user_1977580

You cannot use a parameter there directly (welcome to verilog). In System Verilog it could be solved using a typedef:

  parameter ADDRESS_WIDTH = 9;
  typedef logic [ADDRESS_WIDTH-1:0] awdt_t;
  ...
  Read_mode(awdt_t'(134));

Otherwise, you can use a macro

  `define ADDRESS_WIDTH 9
  ...
  Read_mode(`ADDRESS_WIDTH'd134);
user_11438500
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