Execution order of initial and always blocks in Verilog

user5193259 0
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I'm new to Verilog programming and would like to know how the Verilog program is executed. Does all initial and always block execution begin at time t = 0, or does initial block execution begin at time t = 0 and all always blocks begin after initial block execution? I examined the Verilog program's abstract syntax tree, and all initial and always blocks begin at the same hierarchical level. Thank you very much.

control-flow hdl hardware-programming verilog abstract-syntax-tree
3 Answers

All initial and all always blocks throughout your design create concurrent processes that start at time 0. The ordering is indeterminate as far as the LRM is concerned. But may be repeatable for debug purposes when executing the same version of the same simulation tool. In other words, never rely on the simulation ordering to make you code execute properly.

dave_590

Verilog requires event-driven simulation. As such, order of execution of all 'always' blocks and 'assign' statements depends on the flow of those events. Signal updated one block will cause execution of all other blocks which depend on those signals.

The difference between always blocks and initial blocks is that the latter is executed unconditionally at time 0 and usually produces some initial events, like generation of clocks and/or schedule reset signals. So, in a sense, initial blocks are executed first, before other blocks react to the events which are produced by them.

But, there is no execution order across multiple initial blocks or across initial blocks and always blocks which were forced into execution by other initial blocks.

In addition, there are other ways to generate events besides initial blocks.

userOAN40

In practice, nobody cares, and you shouldn't either.

On actual hardware, the chip immediately after powering-up is very unstable because of the transient states of the power supply circuit, hence its initial states untrustworthy.

The method to ensure initial state in practice is to set them in the initial block as

always @ (event) {
    if(~n_reset) {
        initial_state=0
    } else {
        do_something();
    }
}
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