Mux output with clock select on Verilog

I'm trying to make a mux that will change outputs at every clock edge, but I'm stuck with this output, here's the description

module mux(
    //Units and tens will come from a the output of a decoder, muxdiv is a clock signal that will come from a frequency divider 
    input wire [6:0] tens, [6:0] units, muxdiv, 
    output reg [6:0] pmod
    //pmod is the target 7-segment display.
    );
    
    reg [1:0] select;

    always@(posedge (muxdiv))
    begin
        select = 2'b1;
        if (select == 2'b1)
            pmod = units;
    end
    
    always@(negedge(muxdiv))
    begin
        select = 2'b0;
        if (select == 2'b0)
            pmod = tens;
    end

endmodule

This is my testbench

module mux_tb(

    );
    reg muxdiv;
    reg[6:0] tens;
    reg[6:0] units;
    wire pmod;
    
    mux muxinst(.muxdiv(muxdiv), .tens(tens), .units(units));
    
    initial
    begin
        tens = 7'h3F;
        units = 7'h3F;
        muxdiv = 0;
    end
    
    always #50 muxdiv = ~muxdiv;
    
    always
    begin
        units = 7'h3F;
        #20
        units = 7'h6;    //0000110
        #20
        units = 7'h5B;   //1011011
        #20
        units = 7'h4F;   //1001111
        #20
        units = 7'h66;   //1100110
        #20
        units = 7'h6D;   //1101101
        #20
        units = 7'h7D;   //1111101
        #20
        units = 7'h7;    //0000111
        #20
        units = 7'h7F;   //1111111
        #20
        units = 7'h6F;
    end
    
    always
    begin
        tens = 7'h3F;
        #200
        tens = 7'h6;    //0000110
        #200
        tens = 7'h5B;   //1011011
        #200
        tens = 7'h4F;   //1001111
        #200
        tens = 7'h66;   //1100110
        #200
        tens = 7'h6D;   //1101101
        #200
        tens = 7'h7D;   //1111101
        #200
        tens = 7'h7;    //0000111
        #200
        tens = 7'h7F;   //1111111
        #200
        tens = 7'h6F;
    end
endmodule

And this are the results High impedance at pmod output

I suspect that the mistake comes from the way registers and wires are interacting, but I can't be sure, I was kinda, thrusted into verilog not a week ago.