Can you alias an entity?

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Reading through the LRM, and it appears to imply anything can be aliased, but when I try the following, ActiveHDL tells me a design unit is expected:

entity some_entity is
.....
end entity;

alias another_name is some_entity;

The LRM states (in 6.6.1) that

An object alias is an alias whose alias designator denotes an object (i.e., a constant, a variable, a signal, or a file). A nonobject alias is an alias whose alias designator denotes some named entity other than an object. An alias can be declared for all named entities except for labels, loop parameters, and generate parameters.

Or is it just the case that because an alias is a declarative item, it must exist in an declarative region? But given that an alias takes on the same class as the aliased item, surely it should be allowed in the same region? This appears to compile ok:

package alias_package is
  alias another_name is work.some_entity;
end package;

Explanation for the above request: Lets say I want to rename some_entity, but it is used all over my design. Creating an alias to it would allow this, keeping the old name as an alias to the new one. Using the package would be unsuitable here as it would still require name modification at instantiation.

Is this worthy of a request for the next LRM?

vhdl
1 Answers

Or is it just the case that because an alias is a declarative item, it must exist in an declarative region?

Yes. A design file is comprised of one or more design units and an entity declaration is a design unit. A design unit is comprised of one or more nested declarative regions. The root declarative region (with an optional context clause encompasses the design unit itself and any subordinate secondary design units.

There's no delimiter for declarative regions other than the end of a design unit.

But given that an alias takes on the same class as the aliased item, surely it should be allowed in the same region?

No. A declaration doesn't take effect (it's name doesn't become visible) until after the declaration is complete. Here, after end [entity_simple_name] ;.

A new design unit begins with optional context items (beginning with reserved words library, use or context) followed by a primary unit declaration or secondary unit body (indicated by one of the reserved words entity, architecture, package, configuration, context (here ignoring PSL, tool directives and comments).

Design units are independently analyzed.

The classes of aliases are object and non-object. An alias declaration targets the declaration of a named entity (and some name declarations are implicit).

Is this worthy of a request for the next LRM?

This question is a request for a subjective opinion without a clear use case (providing examples, particularly in a design hierarchy). The reason isn't clear. What work are you trying to avoid?

As an opinion otherwise, no.

There are also parts of the standard that are poorly supported by synthesis vendors that already address modifying binding from the default by exception (configuration declarations containing context specifications or component instantiation with the reserved word configuration).

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