x86

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Are there any modern CPUs where a cached byte store is actually slower than a word store?
user_2241320
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10
2
864
arm cpu-cache x86 cpu-architecture performance
Why stack grows by 16 bytes in this disassembly, when I only have one 4 byte local variable?
user_6685740
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3
2
351
gcc8 calling-convention x86 assembly c
What level of the cache does PREFETCHT2 fetch into?
user_1491380
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4
0
289
amd-processor cpu-cache intel x86 cpu-architecture
Does clflush also remove TLB entries?
user_1491380
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4
2
728
cpu-cache x86 caching performance
Will CPUID serialize speculative data caching?
user_108656220
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3
1
131
cpuid micro-architecture microbenchmark cpu-cache x86
What's the point of the VPERMILPS instruction (_mm_permute_ps)?
user_100615170
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14
1
1035
avx instruction-set x86 assembly
Why jnz requires 2 cycles to complete in an inner loop
user_108656220
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5
2
449
micro-architecture microbenchmark micro-optimization x86
Weird performance effects from nearby dependent stores in a pointer-chasing loop on IvyBridge. Adding an extra load speeds it up?
user_108656220
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7
1
467
micro-architecture microbenchmark micro-optimization x86 assembly
Is mov r64, m64 one cycle or two cycle latency?
user_108656220
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4
1
515
micro-architecture microbenchmark cpu-cache x86 assembly
How to force cpu core to flush store buffer in c?
user_9522680
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5
2
1005
cpu-cache x86 cpu-architecture multithreading c
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