x86

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Building backward compatible binaries with newer CPU instructions support
user_1772750
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4
1
483
compiler-optimization inline-assembly x86 gcc c
What do parentheses surrounding a register mean?
user_53300590
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2
2
2131
addressing-mode att cpu-registers x86 assembly
Why are the code and data segment selectors 0x8 and 0x10 in MIT's JOS Bootloader?
user_41093260
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3
0
400
gdt memory-segmentation osdev x86 assembly
Do x86 instructions require their own encoding as well as all of their arguments to be present in memory at the same time?
user_131812770
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69
1
1569
kvm virtualization paging x86 assembly
What do multiple values or ranges means as the latency for a single instruction?
user_122025360
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2
1
159
micro-optimization x86 assembly cpu-architecture performance
Why use push/pop instead of sub and mov?
user_39685750
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4
1
1097
x86-64 micro-optimization x86 assembly cpu-architecture
Why does DOS set the SP register to 0xFFFE after loading a .COM file?
user_93773020
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11
1
623
x86-16 dos callstack x86 assembly
Intel AVX-512: how to set the EVEX.z bit
user_82769730
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5
1
307
avx512 machine-code x86 assembly
What is clang trying to do optimizing this simple recursive algorithm?
user_5845180
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7
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275
clang x86 assembly c
which MOV instructions in the x86 are not used or the least used, and can be used for a custom MOV extension
user_129244240
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2
1
843
gem5 inline-assembly machine-code x86 gcc
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