x86

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volatile increments with false sharing run slower in release than in debug when 2 threads are sharing the same physical core
user_108512910
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3
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124
false-sharing x86 cpu-architecture c++ performance
QEMU doesn't reboot my OS after resetting via the 8042 PS/2 controller
user_135788960
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3
1
319
multiboot osdev qemu x86 assembly
An i386/x64 pop FS/GS instruction supports a variant where it increments the SP by 32 bits or 64 bits in stead of 16 bits. What is it used for?
user_57404160
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8
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116
i386 x86-64 x86 assembly
Best way to do a packed 16 element blend using SSE
user_31638310
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9
0
258
x86-64 sse intel x86 assembly
Entering protected mode from a DOS program
user_54079470
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2
1
554
protected-mode masm dos x86 assembly
Why any modern x86 masks shift count to the 5 low bits in CL
user_31974200
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4
4
1083
bit-shift cpu-registers x86 assembly cpu-architecture
Are X86 atomic RMW instructions wait free
user_22457070
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4
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624
wait-free lockless atomic x86 concurrency
Why does this assembly code not working to print to VGA text mode video memory?
user_126637440
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3
1
498
bootloader nasm disassembly x86 assembly
Are memory orderings: consume, acq_rel and seq_cst ever needed on Intel x86?
user_9971120
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7
1
678
stdatomic x86 optimization c++ performance
Why syscall/sysret in legacy mode is considered "sufficiently poorly designed"?
user_126977970
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4
1
134
amd-processor operating-system system-calls x86 assembly
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