x86

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The same AVX instruction set code has a huge performance gap between Intel Core and AMD Ryzen
user_125003540
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3
1
487
intrinsics x86 assembly c++ performance
Why RBP instead of another register as a frame pointer?
user_122831810
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2
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391
stack-frame x86-64 pointers x86 assembly
Why isn't INT 31H set up properly even with a DPMI host active?
user_3667540
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4
1
169
windows-3.1 real-mode dos x86 assembly
Conditional jump to memory address
user_122831680
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3
2
534
x86-64 gnu-assembler x86 assembly
How to explicitly load a structure into L1d cache? Weird results with INVD with CR0.CD = 1 on isolated core with/without hyperthreading
user_140908170
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8
1
323
cpu-cache x86 linux-kernel cpu-architecture c
Why is the assembly code generate by hello world in C not having a .code segment nor model tiny like x86 assembly does?
user_134570820
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2
1
125
x86 assembly gcc c
Database for assembly instructions?
user_154146400
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2
2
188
opcode mnemonics x86 assembly
How to disable L3 cache prefetcher on Intel Xeon Scalable Processor?
user_154129820
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3
1
686
msr prefetch cpu-cache intel x86
Signed Multiplication of 1024-bit 2's complement numbers using 32-bit chunks
user_99065730
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2
1
333
twos-complement bigint x86 assembly c
can anyone explain about this XV6 inline asm validateint() test function that uses a pointer as ESP for a system call?
user_131192670
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2
1
206
xv6 inline-assembly x86 assembly c
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