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What is the rationale for setting all SSE/AVX registers call-clobbered in the SysV ABI?
user_17665807
0
•
asked Feb 12, 2022
4
1
144
abi
x86-64
calling-convention
sse
x86
Are the event ratios in Appendix B.8 of Intel's Optimization Reference Manual applicable to other microarchitectures?
user_6573510
0
•
asked Feb 8, 2022
1
0
23
intel-pmu
x86
performance
Bit Hack to get location of bit change
user_288360
0
•
asked Feb 8, 2022
3
2
124
bit
bit-manipulation
x86
Why programmable interval timer cannot work while other device work?
user_13847527
0
•
asked Feb 8, 2022
2
1
78
interrupt
operating-system
x86
assembly
I'd like to make a software which will be executed with BIOS
user_12420001
0
•
asked Feb 8, 2022
2
1
38
bios
bootloader
operating-system
x86
Is the Linux paging model an abstraction?
user_16465739
0
•
asked Feb 5, 2022
2
1
81
addressing-mode
paging
x86
linux-kernel
linux
Intel-x86, confused about the allocation of bytes in the esp register
user_13175761
0
•
asked Feb 3, 2022
1
1
61
x86
assembly
c
How to manually insert a breakpoint that Bochs's built-in debugger will stop at? INT3 doesn't work
user_18089950
0
•
asked Feb 2, 2022
3
1
150
bochs
x86-16
x86
debugging
Did the low register and high register swap places?
user_12713310
0
•
asked Jan 30, 2022
1
1
50
cpu-registers
x86
assembly
arrays
loops
How to make gcc or clang use 64-bit/32-bit division instead of 128-bit/64-bit division when the dividend is 64-bit and the quotient is 32-bit?
user_17665807
0
•
asked Jan 30, 2022
5
1
334
compiler-optimization
clang
x86
gcc
c
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