x86

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Copy bit of one register to another register (x86-64 asm)
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4
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278
micro-optimization bit-manipulation x86 assembly
Are IA-32 segment descriptors that do not cover the full 4GiB linear address space slower?
user_148462760
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2
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43
memory-segmentation x86 cpu-architecture optimization performance
How can I properly emulate x86 with Unicorn in Python?
user_34767870
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2
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200
x86-emulation x86 assembly python
Can L2 software prefetches trigger L2 hardware prefetch?
user_31549960
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7
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114
prefetch x86 cpu-architecture optimization performance
Assembly instruction to alter for spaceship movement (DEC to MOV)
user_182917220
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2
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59
opcode x86 reverse-engineering assembly
Use of sbb instruction and Carry Flag
user_133476220
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2
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159
bigint att x86 assembly
Why does AT&T syntax use parens around DX in IN / OUT instructions like inb (%dx),%al
user_160780980
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1
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121
att x86 assembly gcc
Is it possible to access 4GB memory in v86 mode through the iret instruction?
user_162422780
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2
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57
x86-16 memory-segmentation x86 assembly
Is there a typo/bug in the documentation of the loop instruction?
user_4711290
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77
manual intel x86 assembly
Which alignment causes this performance difference
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perf memory-alignment x86 cpu-architecture performance
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