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Implementing context switch - 2nd function does not run again
user_8293440
0
•
asked Jul 12, 2017
4
1
800
x86-64
inline-assembly
multithreading
c++
Calling printk in a simple IRQ handler crashes the kernel
user_2350670
0
•
asked Jul 10, 2017
3
2
861
page-fault
irq
isr
x86-64
linux-kernel
Meaning of suffix "x" in intrinsics like "_mm256_set1_epi64x"
user_1915854
0
•
asked Jul 8, 2017
7
1
1092
intrinsics
vectorization
x86-64
simd
x86
How is "rax" different from "eax"?
user_4355406
0
•
asked Jul 7, 2017
3
1
2249
x86-64
cpu-registers
x86
assembly
Why does this MOVSS instruction use RIP-relative addressing?
user_3393524
0
•
asked Jul 7, 2017
5
1
6676
relative-addressing
addressing-mode
x86-64
disassembly
assembly
difference between MMX and XMM register?
user_5581182
0
•
asked Jun 1, 2017
34
1
25928
mmx
x86-64
sse
x86
assembly
Why does my disassembled C++ code use the instruction pointer and an offset to get string literals?
user_3124459
0
•
asked May 31, 2017
10
1
401
x86-64
assembly
c++
Moving 2 QWORDs from general purpose registers into an XMM register as high/low
user_4049658
0
•
asked May 30, 2017
3
2
1102
masm
x86-64
sse
assembly
Can we use x86_64 CPU atomics to generate on PCI Express the compound atomic operations?
user_1558037
0
•
asked May 29, 2017
3
1
2016
pci-e
driver
x86-64
linux-device-driver
multithreading
Get size of x86-64 instruction
user_1401690
0
•
asked May 28, 2017
8
2
1655
x86-64
assembly
c
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