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Is gcc-c++ not optimizing atomic operations for current x86-64 processors
user_7156008
0
•
asked Jul 20, 2017
4
2
432
x86-64
atomic
concurrency
assembly
c++
Can't force the use of 64-bit registers in GCC inline assembly
user_8107430
0
•
asked Jul 18, 2017
5
1
1543
x86-64
inline-assembly
gcc
c
Values returned by E820h QuerySystemAddressMap on 4GB+ memory
user_3144770
0
•
asked Jul 16, 2017
4
1
168
bios
x86-64
assembly
memory
How can I accurately benchmark unaligned access speed on x86_64?
user_8157187
0
•
asked Jul 16, 2017
6
3
2715
x86-64
inline-assembly
benchmarking
x86
performance
Fully utilizing pipelines on kaby lake
user_2189500
0
•
asked Jul 16, 2017
8
2
370
avx2
x86-64
micro-optimization
assembly
performance
Set all bits in CPU register to 1 efficiently
user_2428640
0
•
asked Jul 14, 2017
20
2
6899
mips
x86-64
arm
assembly
Why MOV AH,1 is not supported in 64 bit mode of intel microprocessor?
user_5254777
0
•
asked Jul 13, 2017
3
2
1130
x86-64
x86
assembly
Was there a P4 model with double-pumped 64-bit operations?
user_149138
0
•
asked Jul 12, 2017
5
1
750
x86-64
intel
x86
cpu-architecture
Atomic double floating point or SSE/AVX vector load/store on x86_64
user_1915854
0
•
asked Jul 12, 2017
5
2
3482
stdatomic
vectorization
x86-64
assembly
c++
Why is memcmp(a, b, 4) only sometimes optimized to a uint32 comparison?
John_Zwinck_4323
0
•
asked Jul 12, 2017
69
4
5047
compiler-optimization
x86-64
clang
gcc
c
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