x86-64

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Cache coherency(MESI protocol) between different levels of cache namely L1, L2 and L3
user_56805070
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3
1
540
mesi x86-64 cpu-cache cpu-architecture caching
What does `var@GOTPCREL(%rip)` mean?
user_112696570
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5
1
1693
got att x86-64 dynamic-linking assembly
converting ASM instruction RDRand to Win64
user_11140430
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3
1
166
rdrand x86-64 assembly delphi
x86_64 Instruction pipelining: Instruction execution order
user_56805070
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2
1
125
x86-64 instruction-set assembly cpu-architecture
Apparent no-op in Rust assembly output?
user_5656350
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7
1
195
rust x86-64 bit-manipulation assembly
Correlating LLVM IR analysis with final address
user_131693440
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2
1
96
llvm-c++-api llvm-ir x86-64 llvm
Checking for ID flag in RFLAGS using inline assembly in C
user_150485040
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2
1
139
cpuid x86-64 inline-assembly c
GCC optimization flag -O2 makes code much slower that -O0
user_47949370
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6
0
77
x86-64 gcc optimization
Why is EAX being cleared before calling a function if I don't include the header?
user_122831810
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25
1
1821
x86-64 calling-convention assembly c
Use of NASM's __?float?__ macros
user_131880710
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2
1
259
nasm x86-64 floating-point assembly
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