riscv

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Better way to write a few MMIO register bits in RISC-V assembly?
user_50837840
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3
1
108
memory-mapped-io riscv32 riscv assembly
how to get a critical path / bottleneck analysis of FIRRTL code?
user_1247040
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2
1
54
riscv firrtl chisel
Does GCC generate wrong assembly code for the "beq" instruction of riscv?
user_191965360
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3
0
55
riscv gnu-assembler assembly gcc
How to assign data to a register in chisel?
user_191796970
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1
1
36
rocket-chip riscv chisel
RISCV branchless coding
user_3011660
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4
1
190
conditional-move riscv branch-prediction assembly cpu-architecture
Why are linux system calls different across architectures
user_187683300
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2
1
84
riscv system-calls linux-kernel linux
Why does 64 bit RISC-V GCC sign-extends unsigned value after load?
user_4271580
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1
0
95
riscv compilation gcc
Why are periperal registers 16 bit only on 32 bit MCUs such as STM32 and GD32VF103?
user_4271580
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2
2
188
riscv stm32 peripherals microcontroller
Problem with Running gem5: gem5.opt isn't generated after running /usr/bin/env python3.9 $(which scons) build/RISCV/gem5.opt -no-pie
user_160194260
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1
0
26
riscv gem5 scons g++ python-3.x
What if RISC-V function has too many arguments?
user_77953570
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1
1
170
riscv abi calling-convention parameter-passing
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