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Are load and store operations in shared memory atomic?
user_2231159
0
•
asked Jun 11, 2022
2
1
91
ptx
atomic
multicore
cuda
Understanding the parameters of PTX instruction mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32
user_17457332
0
•
asked Jan 12, 2022
2
1
264
ptx
matrix-multiplication
inline-assembly
cuda
What does it mean when a variable "has been demoted" in the PTX?
user_1593077
0
•
asked Jul 27, 2021
2
1
101
ptx
nvcc
cuda
How to compile cuda code with calling one function twice inside one method?
user_3297655
0
•
asked Feb 28, 2021
2
1
78
ptx
cuda
Ray triangle intersection intrinsic in CUDA and other OptiX components
user_10642613
0
•
asked Dec 31, 2020
4
1
279
optix
ptx
raytracing
cuda
Differences between NVCC and NVRTC on compilation to PTX
user_3136474
0
•
asked Apr 1, 2020
2
1
2052
ptx
nvrtc
cuda
c++
Some intrinsics named with `_sync()` appended in CUDA 9; semantics same?
user_1593077
0
•
asked Sep 27, 2017
3
1
551
gpu-warp
ptx
cuda
What's the most efficient way to calculate the warp id / lane id in a 1-D grid?
user_1593077
0
•
asked Jun 2, 2017
12
2
5875
ptx
cuda
optimization
CUDA/PTX 32-bit vs. 64-bit
user_3076234
0
•
asked Dec 17, 2013
6
1
2719
ptx
nvcc
cuda
How to output C/C++ annotated PTX in CUDA 4.1/4.2/5.0
user_724461
0
•
asked Jul 13, 2012
10
3
1083
ptx
cuda
llvm
1
(current)
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