micro-optimization

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Why does gcc use btq in conjunction with btcq when conditionally set a bit in a uint64_t * memory region
user_113221310
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5
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145
x86-64 micro-optimization assembly gcc c
Bottleneck when using indexed addressing modes
user_104619730
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3
1
172
addressing-mode x86-64 micro-optimization intel cpu-architecture
Why this unnecessary MOVAPD copy in gcc 9.1, in a tiny function
user_58788760
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5
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139
x86-64 micro-optimization sse assembly gcc
Swap two registers in aarch64
user_6349190
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1355
arm64 swap micro-optimization assembly
Does cmpxchg write destination cache line on failure? If not, is it better than xchg for spinlock?
user_29450270
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5
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667
compare-and-swap micro-optimization cpu-cache x86 assembly
What is the correct and optimal implementation of atomic_ref and atomic with padding bits?
user_29450270
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3
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307
stdatomic c++20 micro-optimization x86
In x86-64 asm: is there a way of optimising two adjacent 32-bit stores / writes to memory if the source operands are two immediate values?
user_63536110
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8
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227
x86-64 micro-optimization assembly optimization
What is an efficent way to compute floor(log(m / n)), where m and n are integers?
user_56026890
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8
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103
micro-optimization assembly optimization c
Is movzbl followed by testl faster than testb?
user_75090650
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3
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162
x86-64 micro-optimization x86 assembly performance
What is the fastest way to swap the bytes of an unaligned 64 bit value in memory?
user_24088670
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957
x86-64 micro-optimization endianness assembly performance
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