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micro-optimization
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Should combining memory fence for mutex acquire-exchange loop (or queue acquire-load loop) be done or should it be avoided?
user_2945027
0
•
asked Jun 11, 2020
2
2
1518
memory-barriers
arm
micro-optimization
cpu-architecture
How to instruct MS Visual C++ compiler to use an uninitialized __m512i register
user_1892814
0
•
asked Jun 9, 2020
4
1
177
avx512
intrinsics
micro-optimization
visual-c++
c++
Mixing SSE with AVX128 for shorter instructions?
user_459150
0
•
asked Jun 7, 2020
3
1
255
avx
micro-optimization
sse
x86
assembly
How can one figure out if a loop is being entered with a 16 byte aligned address in x86-64 assembly?
user_5626290
0
•
asked May 15, 2020
2
1
166
x86-64
micro-optimization
memory-alignment
assembly
optimization
Is it faster to prepend to a string with substr?
user_124486
0
•
asked May 7, 2020
6
1
117
substr
micro-optimization
benchmarking
perl
Are two store buffer entries needed for split line/page stores on recent Intel?
user_149138
0
•
asked Apr 13, 2020
9
0
170
micro-architecture
micro-optimization
intel
x86
cpu-architecture
Set an XMM register to a repeating byte pattern (broadcast a constant byte)
user_12202536
0
•
asked Mar 29, 2020
2
1
598
micro-optimization
sse2
sse
assembly
What do multiple values or ranges means as the latency for a single instruction?
user_12202536
0
•
asked Mar 29, 2020
2
1
159
micro-optimization
x86
assembly
cpu-architecture
performance
Why use push/pop instead of sub and mov?
user_3968575
0
•
asked Mar 26, 2020
4
1
1097
x86-64
micro-optimization
x86
assembly
cpu-architecture
how to optimize multi independent Conditional branch in Compare Function?
user_8593015
0
•
asked Mar 24, 2020
4
2
307
branch-prediction
micro-optimization
comparison
c++
performance
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