cpu-cache

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Is there any way to tell an x86 to discard dirty cache lines without writing them?
user_54790040
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3
0
99
x86-64 cpu-cache assembly
How to explain poor performance on Xeon processors for a loop with both sequential copy and a scattered store?
user_142344440
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14
1
649
amd-processor cpu-cache intel cpu-architecture performance
What is the purpose of invalidating D-cache when D-cache is off?
user_29061000
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2
1
661
arm64 cpu-cache assembly linux-kernel caching
Width of bus betwen cpu cache and cpu
user_122920000
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2
1
562
amd-processor cpu-cache x86 cpu-architecture cpu
Am I correctly reasoning about cache performance?
user_42586290
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3
1
113
perf cpu-cache x86 multithreading c++
Does cmpxchg write destination cache line on failure? If not, is it better than xchg for spinlock?
user_29450270
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5
2
667
compare-and-swap micro-optimization cpu-cache x86 assembly
What happens for a RIP-relative load next to the current instruction? Cache hit?
user_100905580
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2
1
91
x86-64 cpu-cache x86 assembly cpu-architecture
Reducing bus traffic for cache line invalidation
user_458430
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7
1
205
memory-barriers memory-model cpu-cache cpu-architecture multithreading
Is there such thing as a semi-shared cache?
user_94063720
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2
1
59
cpu-cache memory processor cpu caching
Do store instructions block subsequent instructions on a cache miss?
user_55016750
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5
1
212
cpu-cache x86 concurrency cpu-architecture c++
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