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What's the difference between the CMP and TST instructions in ARM?
user_9475482
0
•
asked Jan 10, 2019
3
1
11036
arm
assembly
(How) can I predict the runtime of a code snippet using LLVM Machine Code Analyzer?
user_750378
0
•
asked Jan 9, 2019
6
1
1332
llvm-mca
assembly
c
c++
performance
Weird performance effects from nearby dependent stores in a pointer-chasing loop on IvyBridge. Adding an extra load speeds it up?
user_10865622
0
•
asked Jan 8, 2019
7
1
467
micro-architecture
microbenchmark
micro-optimization
x86
assembly
Is mov r64, m64 one cycle or two cycle latency?
user_10865622
0
•
asked Jan 7, 2019
4
1
515
micro-architecture
microbenchmark
cpu-cache
x86
assembly
How to use MIPS load word
user_1326868
0
•
asked Jan 6, 2019
3
1
3337
mips
assembly
memory
For temporary registers in the asm statement, should I use clobber or dummy output?
user_4460514
0
•
asked Jan 6, 2019
3
1
1508
inline-assembly
assembly
gcc
DMB instructions in an interrupt-safe FIFO
user_1488067
0
•
asked Jan 6, 2019
6
3
910
c11
atomic
assembly
gcc
c
Useless test instruction?
user_2406992
0
•
asked Jan 5, 2019
33
1
1594
jvm-hotspot
jit
jvm
assembly
java
Hard to debug SEGV due to skipped cmov from out-of-bounds memory
user_2657597
0
•
asked Jan 5, 2019
7
2
412
x86-64
assembly
gdb
Why dependency in a loop iteration can't be executed together with the previous one
user_10865622
0
•
asked Jan 5, 2019
3
1
111
micro-architecture
micro-optimization
x86
assembly
performance
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