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Understanding micro-architectural causes for longer code to execute 4x faster (AMD Zen 2 architecture)
user_393756
0
•
asked Mar 2, 2021
4
1
112
amd-processor
x86
assembly
cpu-architecture
c++
C# compiled into assembly. Why does it take longer to run fewer assembly instructions?
user_103959
0
•
asked Jan 23, 2021
4
0
90
amd-processor
x86-64
assembly
cpu-architecture
c#
What is Causing Big Performance Differential Between Different Zen 1 Processors for a Simple Benchmark?
user_3360945
0
•
asked Dec 3, 2020
4
0
117
amd-processor
cpu-cache
cpu-architecture
caching
performance
Why adox and adcx don't play well together on Ryzen?
user_14724380
0
•
asked Nov 28, 2020
5
1
211
adx
gmp
amd-processor
x86
cpu-architecture
What is the XOP prefix in an instruction?
user_11520390
0
•
asked Nov 27, 2020
2
0
155
amd-processor
instructions
machine-code
x86
assembly
Why are set cache associativity in modern day processors 8-way set associative?
user_13170122
0
•
asked Nov 12, 2020
3
1
1092
amd-processor
cpu-cache
intel
cpu-architecture
caching
Intel OpenMP library slows down memory bandwidth significantly on AMD platforms by setting KMP_AFFINITY=scatter
user_4896631
0
•
asked Oct 18, 2020
4
1
845
amd-processor
icc
hpc
openmp
affinity
Visual Studio: Xamarin - Error starting Android Emulator
user_394087
0
•
asked Sep 21, 2020
17
10
17521
amd-processor
xamarin
visual-studio-2019
android-emulator
How to explain poor performance on Xeon processors for a loop with both sequential copy and a scattered store?
user_14234444
0
•
asked Sep 7, 2020
14
1
649
amd-processor
cpu-cache
intel
cpu-architecture
performance
Width of bus betwen cpu cache and cpu
user_12292000
0
•
asked Aug 3, 2020
2
1
562
amd-processor
cpu-cache
x86
cpu-architecture
cpu
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