I simulated a 4-bit ripple adder made up of 4 full adders in Verilog. Here, I'm trying to understand what is happening with Cout. Cout stands for carry output. I can't explain how values E and F were obtained in Cout.
This is ripple_adder.v
module full_adder( A, B, CIN, Q, COUT );
input A, B, CIN;
output Q, COUT;
assign Q = A ^ B ^ CIN;
assign COUT = (A & B) | (B & CIN) | (CIN & A);
endmodule
module adder_ripple( a, b, q );
input [3:0] a, b;
output [3:0] q;
wire [3:0] cout;
full_adder add0 ( .Q(q[0]), .COUT(cout[0]),
.A(a[0]), .B(b[0]), .CIN( 1'b0) );
full_adder add1 ( .Q(q[1]), .COUT(cout[1]),
.A(a[1]), .B(b[1]), .CIN(cout[0]) );
full_adder add2 ( .Q(q[2]), .COUT(cout[2]),
.A(a[2]), .B(b[2]), .CIN(cout[1]) );
full_adder add3 ( .Q(q[3]), .COUT(cout[3]),
.A(a[3]), .B(b[3]), .CIN(cout[2]) );
endmodule
This is test bench for ripple_adder.v
`timescale 1ps/1ps
module adder_ripple_tp;
reg [3:0] a, b; // reg declaration for input
wire [3:0] q; // wire declaration for output
parameter STEP = 100000;
adder_ripple adder_ripple( a, b, q );
initial begin
$dumpfile("adder_ripple.vcd");
$dumpvars(0, adder_ripple_tp);
a = 4'h0; b = 4'h0;
#STEP a = 4'h5; b = 4'ha;
#STEP a = 4'h7; b = 4'ha;
#STEP a = 4'h1; b = 4'hf;
#STEP a = 4'hf; b = 4'hf;
#STEP $finish;
end
initial $monitor( $stime, " a=%h b=%h q=%h", a, b, q );
endmodule
The wave looks like this:
Can someone help me understand it?
