Parallel In Parallel Out Register

Question

The PIPO module implements a Parallel In Parallel Out Register. It takes in these inputs (clk,reset,pipo_in,load) and an output (pipo_out).

If reset signal is HIGH, pipo_out = 0.

If load signal is HIGH, whatever new pipo_in is coming will be the output.

But, if the load signal is not high, then pipo_out should show the previously output value. Now what I'm doing is pipo_out = 0;

What changes can be done, so that when the load signal is not high, then pipo_out should show the previously output value.

module PIPO (clk,reset,pipo_in,load,pipo_out);

input clk;
input reset;
input [3:0] pipo_in;
input load;
output reg [3:0] pipo_out;


always @(posedge clk) 
begin
    if (reset) 
    begin
        pipo_out = 4'b0000;
    end
    else if (load)
    begin
        pipo_out = pipo_in;
    end
    else begin
        pipo_out = 4'b0000;
    end
end

endmodule

here is the testbench:

`include "PIPO.v"

module PIPO_tb;

    reg clk;
    reg reset;
    reg  [3:0]pipo_in;
    reg load;
    wire [3:0]pipo_out;
    
    PIPO iPIPO (.*);   

    initial begin
    clk=0;
    forever
    #5 clk= ~clk;
    end 
    
    initial begin
        $monitor("Reset=%b Input=%b, load=%b output=%b",reset,pipo_in,load,pipo_out);
        $dumpfile("PIPO_tb.vcd");
        $dumpvars(0, PIPO_tb);

       
        reset=0; pipo_in =4'b1001;load=1;#10;
        reset=0; pipo_in =4'b1011;load=1;#10;
        reset=0; pipo_in =4'b1101;load=1;#10;
        reset=0; pipo_in =4'b0001;load=0;#10;
        reset=0; pipo_in =4'b1111;load=1;#10;
        reset=0; pipo_in =4'b1010;load=1;#10;

        

        #200;
        $finish;
    end
endmodule

user_197758 · Answer

To retain the previously loaded value, simply remove the else clause:

always @(posedge clk)
begin
    if (reset)
    begin
        pipo_out <= 4'b0000;
    end
    else if (load)
    begin
        pipo_out <= pipo_in;
    end
end

For sequential logic, you should use nonblocking (<=) assignments.

Parallel In Parallel Out Register

1 Answers