What instruction set does SFENCE belong to?

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I've been doing a good amount of research on AMD64 (x86-64) instructions, and its been kind of confusing. A lot of the time official CPU documentation doesn't designate instruction as part of a specific set, and the internet is sometimes split on which instruction set a specific instruction belongs to. One example of this is SFENCE, with some sources claiming that it's part of EMMX and others claiming it's part of SSE.

I'm trying to organize all of them in a spreadsheet to help with learning, but these inconsistencies are incredibly frustrating in a field that is famously technical and precise.

mmx amd-processor x86-64 sse assembly
1 Answers

EMMX is a subset of SSE, and sfence is part of both of them.

AMD did not immediately support all SSE instructions, but at first took a subset of it that did not require the new XMM registers (see near the bottom of the PDF), which became known as EMMX. That included for example pavgb mm0, mm1 (but not pavgb xmm0, xmm1), and also sfence.

All instructions that are in EMMX are also in SSE, processors that support SSE can execute EMMX code regardless of whether they "explicitly" support EMMX (which has a dedicated CPUID feature flag). The Zen 1 aka Summit Ridge you linked, supports EMMX implicitly: it does not have the corresponding feature flag set, but since it supports SSE, it also ends up supporting EMMX. Before Zen, AMD processors with SSE used to set the EMMX feature flag as well.

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