Use only a subset of output port bits?

user_7453757 0
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This is a general Verilog question. Say I have instantiated some module with a 32-bit output port, but I'm only interested in the low 8-bits.

wire [7:0] my_8bits;
some_module inst (
  ...
  .out_32bit_port(my_8bits);   // out_32bit_port is a 32-bit output port
);

This will generate a warning that the signal I have connected to the output port does not match the port size. Of course, in this case I am completely aware of what I've done and I can just ignore the warning.

How can I code this to eliminate all warnings?

verilog
1 Answers

One way to eliminate the width mismatch warning is to create a 32-bit wire, connect it to the instance, then drive your 8-bit wire as a continuous assignment:

wire [31:0] out_32bit_port;
wire [7:0] my_8bits = out_32bit_port[7:0];

some_module inst (
      .out_32bit_port (out_32bit_port)
);

Another way is to create a 24-bit wire and concatenate it with the 8-bit wire in the instance port connection:

wire [7:0] my_8bits;
wire [23:0] unused;

some_module inst (
      .out_32bit_port ({unused, my_8bits})
);
user_1977580
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