Clarification on uses of posedge in "if"

user_17958254 0
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I'm trying my hand at teaching myself some Verilog. I'm trying to make a mod-10 counter that iterates every second or so. The code I'm trying to modify is some I found on an old forum.

I've tried to use a secondary counter that iterates on every rising edge of the 26th bit of "counter". Am I not allowed to check for such an event? How might I do this in other ways?

always @(posedge clk) begin
    if (!enable) begin 
        counter <= counter + 1;
        
        if (posedge counter[26]) begin 
            seven_output = seven_output + 1;  //iterate the cumulative output state every second ish
        end     
    end
end

Here, seven_output is just another counter whose purpose will be to iterate as described and will be passed to a separate module whose job it will be to determine what combined state of LEDs to return.

The only error description I'm being given is

Line 73: Syntax error near "posedge".

Line 73 is the inner-most if statement.

verilog
1 Answers

You get the syntax error because the usage of the posedge keyword is illegal in the following line:

    if (posedge counter[26]) begin

It is illegal because there is no timing event control. For example, @(posedge something) uses the posedge keyword along with an edge control construct: @( ).

Instead of using posedge there, you should create separate logic for an edge detector of the count[26] signal; let's call it pe_count26.

Furthermore, I recommend separating your 2 counters into 2 separate always blocks.

always @(posedge clk) begin
    if (!enable) begin 
        counter <= counter + 1;    
    end
end

always @(posedge clk) begin
    if (pe_count26) begin 
        seven_output <= seven_output + 1;
    end
end

It is a recommended good coding practice to use nonblocking assignments (<=) for sequential logic. I changed your seven_output assignment accordingly.

user_1977580
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