Modulating a signal on-off at 10kHz

user_13218692 0
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I have written the code for the input clk = 10MHz and output_clk = 5MHz. I want to modulate the output_clk on-off at 10kHz as shown in the example signal. But, my current code only modifies the output_clk to be 10kHz rather than modulating the signal on-off at 10kHz while output_clk remains 5MHz. Any suggestions how to achieve the same?

Please see the example output_clk signal I want as the output.

// mclk1 = 10MHz
always#(50)
begin
    mclk1 <= ~mclk1;
end

reg [31:0]count_500;

always@(posedge mclk1)
begin
  if (count_500 == 500-1)
  begin
      mdata1 <= ~mdata1;
      count_500 <= 0;
  end
  else
  begin
      count_500 <= count_500 + 1;
  end
end

enter image description here

verilog
1 Answers

You can create a new signal which follows mclk1 but is gated by the 10kHz signal:

wire mclk1gated = mdata1 ? mclk1 : 0;

enter image description here

Here is a complete code example:

module tb;

bit mclk1,mdata1;

// mclk1 = 10MHz
always#(50)
begin
    mclk1 <= ~mclk1;
end

reg [31:0]count_500=0;

always@(posedge mclk1)
begin
  if (count_500 == 500-1)
  begin
      mdata1 <= ~mdata1;
      count_500 <= 0;
  end
  else
  begin
      count_500 <= count_500 + 1;
  end
end

wire mclk1gated = mdata1 ? mclk1 : 0;

initial begin
    #300us $finish;
end

endmodule
user_1977580
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