OR together output of parameterized-instanced modules

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In SomeModule want to create an output hitOut which is a logical OR of the hit output of each of a parameterized number of instanced SomeSubModule:

some_sub_module.v

module SomeSubModule(
    hit
);

output reg hit;

some_module.v

module SomeModule(
    hitOut
);

parameter INSTANCE_COUNT = 2;
    
output reg hitOut;
    
SomeSubModule subModule [INSTANCE_COUNT-1:0] (

    // NOTE: Here, I want the value of hitOut to be the logical
    // OR of every instanced submodule's output `hit`
    // ie: 
    // hitOut <= subModule[1].hit | ... | subModule[INSTANCE_COUNT-1].hit
    .hit(hitOut)
);
system-verilog verilog
1 Answers

Create an n-bit wire, connect it to the instance array output port, then bit-wise OR the bits:

module SomeModule(
    hitOut
);

parameter INSTANCE_COUNT = 2;
    
output hitOut;

wire [INSTANCE_COUNT-1:0] hit;
assign hitOut = |hit;
    
SomeSubModule subModule [INSTANCE_COUNT-1:0] (
    .hit (hit)
);
user_1977580
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