I want to give various values in one vector

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    module processor_testbench (
           input [7:0]  o_cmd_status_reg,                                   
           input          o_start_ack,                                        
                                                                                                                 
           output  reg [7:0]  i_transmit_data, // transmit data port              
           input    o_transmit_data_request, // transmit data required 

           output   reg i_rst_n,
           output   reg i_clk
    );

    initial begin
       i=1'b0;
    end

     initial begin    //-> Where the problem is
        @(posedge(o_start_ack));
        i=i+1;
        if(i==1)
        i_transmit_data = 8'bxxx00000;
        else if(i==2)
        i_transmit_data=8'b00000000;
        else if(i==3)
        i_transmit_data=8'b11110000;
        else if(i==4)
        i_transmit_data=8'b00000000;
        //stop trasmission @start acknowledge
    end

    endmodule

I want to see the result (simulation) when the o_start_ack become rising edge.

i_transmit_data is changing

8'bxxx00000 -> 8'b00000000 -> 8'b11110000 -> 8'b00000000

But, the simulation shows only 8'bxxx00000.

Codes that are not used in this case are removed by me.

How can I make i_transmit_data have various value?

verilog
1 Answers

Change your second initial block to an always block:

 always begin
     @(posedge(o_start_ack));
     i=i+1;
     // ...

The problem with your code is that the initial block only waits for one posedge of the o_start_ack signal. Once it sees the 1st posedge, it sets i=1 and i_transmit_data=8'bxxx00000, then the block stops executing.

Using an always block allows the code to execute every time there is a posedge of o_start_ack.

user_1977580
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